Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask may contain a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction. Since, in general, the projection system will have a magnification factor M (generally <1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as described herein can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g., an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc.
For the sake of simplicity, the projection system may hereinafter be referred to as the “lens”; however, this term should be broadly interpreted as encompassing various types of projection systems, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a “lens”. Further, the lithographic apparatus may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441, incorporated herein by reference.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. The design rule limitations are typically referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit.
Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask). However, as the size of lithographically fabricated structures decrease, and the density of the structures increases, the cost and complexity of designing masks additionally increases. That is, as the demand continues for higher performance of semiconductor devices, the design rule shrink rate is outpacing the progress of both of the exposure wavelength reduction and the advancement of high Numerical Aperture (NA) lenses. Therefore, resolution enhancement techniques have been indispensable in low k1 systems. Types of enhancement techniques include optical proximity correction (OPC) and the optimization of the lithographic apparatus, especially the optimization of the NA and partial coherence factor (sigma). These techniques help to overcome certain proximity effects; however, they are manually performed.
Moreover, OPC techniques include feature biasing and strategic placement of sub-lithographic features on the original mask pattern to compensate for proximity effects, thereby improving the final transferred circuit pattern. Sub-resolution assist features, or scattering bars, have been used as a means to correct for optical proximity effects and have been shown to be effective for increasing the overall process window (i.e., the ability to consistently print features having a specified CD regardless of whether or not the features are isolated or densely packed relative to adjacent features). The scattering bars function to change the effective pattern density (of the isolated or less dense features) to be more dense, thereby negating the undesirable proximity effects associated with printing of isolated or less dense features.
For the intermediate pitch features pitches, where there is no room to insert a SB, a typical method of optical proximity correction (OPC) is to adjust the feature edges (or apply bias) so that the printed feature width is closer to the intended width. In order for the use of the sub-resolution features and/or feature biasing to be effective for minimizing optical proximity effects, an operator having a substantial amount of knowledge regarding mask design and the printing process, as well as a substantial amount of experience, is required to modify the mask design to include the subresolution features and/or the adjustment of feature edges (biasing) if the desired goal is to be obtained. Indeed, even when an experienced operator performs this task, it is often necessary to conduct a “trial and error” process in order to properly position the subresolution features to obtain the desired corrections. This trial and error process, which can entail repeated mask revisions followed by repeated simulations, can become both a time consuming and costly process.
In accordance with the foregoing description, there develops a systematic way in which designers optimize a mask pattern. FIG. 13 illustrates a flow chart of this systematic way. In S200, the device layout is examined, to identify a critical pitch (S202). Accordingly, adjustment is made to NA, sigma outer, and sigma inner parameters for a given lithographic apparatus (S204). Based on these parameters, an aerial image may be generated by a simulator for a given mask pattern to identify significant proximity effects for the given pattern. These effects may be addressed by scatter bar treatment to the mask, OPC treatment to adjust the pattern or a combination of both (S206). Still with scatter bar treatment and/or OPC treatment, an optimized bias and OPC treatment is still dependent on the parameters of the given lithographic apparatus such as NA, sigma-outer and sigma-inner. If changed, the routine has to be repeated for the mask. Often, this trial and error process is very time consuming to manually perfect for a given mask, and is primarily dependent on the skill of the designer manually adjusting parameters of the lithographic apparatus and performing the various treatments for addressing optical proximity effects.
Accordingly, there exists a need to create a method or routine that can optimize lithographic apparatus parameters and optimally configure biasing utilizing OPC.